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s
in
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p
ab
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ta
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o
v
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tr
ad
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n
al
p
r
o
ce
s
s
o
r
s
[
1
]
,
[
2
]
.
T
h
ese
d
ev
ices
e
x
ce
l
i
n
ef
f
icie
n
tl
y
h
a
n
d
li
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-
th
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o
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g
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p
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k
s
w
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m
ai
n
tai
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lo
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co
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s
u
m
p
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m
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id
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y
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m
s
a
n
d
co
m
m
u
n
icatio
n
p
r
o
to
co
ls
[
1
]
.
Fu
r
th
er
m
o
r
e,
t
h
e
i
n
teg
r
atio
n
o
f
DSP
b
lo
ck
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o
n
SP
AR
T
A
N
FP
GAs
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n
h
a
n
ce
s
t
h
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ab
ilit
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to
ac
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ler
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co
m
p
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ta
tio
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h
ea
v
y
p
r
o
ce
s
s
es,
s
u
ch
as
co
n
v
o
lu
tio
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al
n
e
u
r
al
n
et
w
o
r
k
(
C
NN)
in
f
er
en
ce
,
h
ig
h
li
g
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tin
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th
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g
r
o
w
in
g
i
m
p
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r
tan
ce
i
n
m
o
d
er
n
h
ar
d
w
ar
e
ac
ce
ler
atio
n
[
2
]
,
[
3
]
.
T
h
is
p
r
o
j
ec
t
em
p
h
a
s
i
ze
s
th
e
FP
GA
-
b
ased
g
en
er
atio
n
o
f
an
alo
g
w
a
v
e
f
o
r
m
s
u
s
i
n
g
d
ir
ec
t
d
ig
ital
s
y
n
t
h
e
s
is
(
DDS)
,
a
tech
n
iq
u
e
w
id
el
y
r
ec
o
g
n
ized
f
o
r
its
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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2
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4864
I
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R
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&
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b
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Vo
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,
No
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3
,
No
v
e
m
b
er
20
25
:
597
-
604
598
ab
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to
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eq
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DDS
allo
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g
en
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w
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ian
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m
a
k
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it
id
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f
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r
ap
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s
in
co
m
m
u
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ica
tio
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s
y
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te
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s
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in
s
tr
u
m
en
tatio
n
,
a
n
d
s
ig
n
al
p
r
o
ce
s
s
i
n
g
[
4
]
.
T
h
e
aim
o
f
th
i
s
p
r
o
j
ec
t
is
t
o
i
m
p
le
m
e
n
t
a
s
ig
n
al
g
e
n
er
ato
r
o
n
th
e
SP
A
R
T
AN
FP
GA
u
s
in
g
th
e
DDS
tech
n
iq
u
e
to
cr
ea
te
h
ig
h
-
q
u
al
it
y
an
alo
g
w
av
e
f
o
r
m
s
.
B
y
ex
p
lo
itin
g
th
e
p
ar
a
llel
p
r
o
ce
s
s
in
g
,
r
ec
o
n
f
i
g
u
r
ab
le
ar
ch
itect
u
r
e,
an
d
lo
o
k
-
u
p
tab
le
(
L
UT
)
ca
p
ab
ilit
ies o
f
th
e
FP
GA
,
t
h
is
d
es
ig
n
p
r
o
v
id
es si
g
n
i
f
ica
n
t a
d
v
a
n
tag
e
s
i
n
ter
m
s
o
f
f
le
x
ib
ili
t
y
,
p
r
ec
is
io
n
,
an
d
s
ca
lab
ilit
y
co
m
p
ar
ed
to
tr
ad
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n
al
w
av
e
f
o
r
m
g
en
er
ato
r
s
[
5
]
.
A
d
d
itio
n
all
y
,
t
h
e
FP
GA's
ca
p
ab
ilit
ies
allo
w
r
ea
l
-
t
i
m
e
m
o
d
i
f
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n
s
o
f
s
ig
n
al
p
ar
a
m
eter
s
,
s
u
c
h
as
f
r
eq
u
en
c
y
a
n
d
p
h
ase,
w
h
ic
h
ar
e
cr
u
cial
in
ad
v
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ce
d
s
ig
n
al
p
r
o
ce
s
s
i
n
g
ap
p
licatio
n
s
[
6
]
,
[
7
]
.
T
o
ac
h
iev
e
p
r
ec
is
e
co
n
tr
o
l
o
f
th
e
o
u
tp
u
t
p
h
ase
d
u
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f
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eq
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en
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y
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w
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h
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n
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tr
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s
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d
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h
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n
ce
p
h
ase
n
o
is
e
w
h
ile
i
m
p
r
o
v
i
n
g
f
r
eq
u
en
c
y
ag
i
lit
y
,
a
n
o
n
-
li
n
ea
r
d
ig
ital
d
esig
n
tec
h
n
iq
u
e
is
em
p
lo
y
ed
[
8
]
.
T
h
is
m
et
h
o
d
g
en
er
ate
s
an
a
lo
g
w
a
v
ef
o
r
m
s
u
s
in
g
s
to
r
ed
d
ig
ital
s
a
m
p
les
f
r
o
m
a
L
UT
th
at
co
n
tai
n
s
d
i
g
ital
d
ata
o
f
a
s
in
u
s
o
id
al
w
av
e
f
o
r
m
[
9
]
,
[
1
0
]
.
B
y
s
eq
u
en
t
iall
y
r
ea
d
in
g
th
ese
v
alu
e
s
an
d
s
en
d
i
n
g
t
h
e
m
to
th
e
in
p
u
t
o
f
a
d
ig
ital
-
to
-
a
n
alo
g
co
n
v
er
ter
(
D
AC
)
,
th
e
s
y
s
te
m
s
y
n
t
h
e
s
izes
an
d
o
u
tp
u
t
s
a
s
m
o
o
t
h
s
in
u
s
o
i
d
al
s
ig
n
al
[
1
1
]
.
T
o
ac
h
iev
e
t
h
is
,
w
e
i
m
p
le
m
e
n
ted
a
v
er
y
h
i
g
h
s
p
ee
d
in
teg
r
ated
cir
cu
it
h
ar
d
w
ar
e
d
escr
ip
tio
n
lan
g
u
a
g
e
(
VHD
L
)
p
r
o
g
r
am
t
h
at
co
n
s
tr
u
c
ts
a
r
ea
d
-
o
n
l
y
m
e
m
o
r
y
(
R
OM
)
co
n
f
i
g
u
r
ed
as a
L
UT
s
p
ec
if
icall
y
d
es
i
g
n
ed
f
o
r
s
in
u
s
o
id
al
w
a
v
e
f
o
r
m
g
e
n
er
atio
n
.
I
n
o
r
d
er
to
m
a
x
i
m
ize
ef
f
icie
n
c
y
an
d
r
ed
u
ce
th
e
u
s
ag
e
o
f
t
h
e
FP
GA’
s
g
e
n
er
al
lo
g
ic
r
es
o
u
r
ce
s
,
w
e
to
o
k
ad
v
an
tag
e
o
f
t
h
e
Xilin
x
Sp
ar
tan
-
6
FP
G
A
’
s
e
m
b
ed
d
ed
B
lo
ck
R
A
M
(
B
R
A
M)
.
T
h
is
allo
w
ed
u
s
to
m
o
d
el
th
e
R
OM
i
n
a
w
a
y
t
h
at
m
i
n
i
m
ized
th
e
i
m
p
ac
t
o
n
th
e
d
ev
i
ce
'
s
lo
g
ical
r
eso
u
r
ce
s
,
o
p
ti
m
i
zin
g
b
o
th
m
e
m
o
r
y
u
s
a
g
e
an
d
p
er
f
o
r
m
an
ce
[
1
2
]
.
B
y
u
s
i
n
g
B
R
A
M
f
o
r
th
e
R
O
M,
w
e
w
er
e
ab
le
to
cr
ea
te
a
c
o
m
p
ac
t
an
d
ef
f
icie
n
t
d
esig
n
th
at
m
ai
n
tai
n
s
h
ig
h
ac
cu
r
ac
y
in
w
a
v
ef
o
r
m
g
en
er
atio
n
w
i
th
o
u
t
co
m
p
r
o
m
is
i
n
g
th
e
FP
GA’
s
p
r
o
ce
s
s
in
g
ca
p
ab
ilit
ies f
o
r
o
th
er
tas
k
s
.
T
h
e
d
esig
n
w
as
p
r
o
g
r
a
m
m
e
d
an
d
s
y
n
th
e
s
ized
w
it
h
i
n
th
e
Xilin
x
I
SE
Desig
n
Su
ite,
a
r
o
b
u
s
t
d
ev
elo
p
m
en
t
e
n
v
ir
o
n
m
en
t
t
h
a
t
p
r
o
v
id
es
ex
ten
s
iv
e
s
u
p
p
o
r
t
f
o
r
th
e
Sp
ar
tan
-
6
s
er
ies.
T
h
is
t
o
o
l
ch
ain
f
ac
il
itated
th
e
i
m
p
le
m
e
n
tat
io
n
,
s
i
m
u
latio
n
,
an
d
v
er
if
ica
tio
n
o
f
o
u
r
d
esi
g
n
,
e
n
s
u
r
i
n
g
t
h
at
i
t
m
e
t p
er
f
o
r
m
an
ce
cr
iter
ia
w
h
ile
m
ai
n
tai
n
in
g
e
f
f
icien
t r
eso
u
r
ce
u
s
a
g
e
o
n
t
h
e
FP
GA
[
1
3
]
,
[
1
4
]
.
T
o
co
n
v
er
t
th
e
d
i
g
ital
s
a
m
p
les
s
to
r
ed
in
th
e
L
UT
in
to
an
a
n
alo
g
s
i
g
n
al,
w
e
u
s
ed
a
n
8
-
b
it
m
o
n
o
lit
h
ic
DAC,
s
p
ec
if
icall
y
t
h
e
D
AC
0
8
0
8
m
o
d
el.
T
h
is
D
A
C
o
p
er
ates
w
i
th
±
5
V
p
o
w
er
s
u
p
p
lies
,
en
s
u
r
i
n
g
ac
c
u
r
ate
co
n
v
er
s
io
n
o
f
d
ig
ital
d
ata
in
to
an
an
alo
g
s
i
g
n
al
[
1
5
]
.
W
ith
th
is
co
n
f
i
g
u
r
at
io
n
,
w
e
w
er
e
ab
le
to
ac
h
iev
e
h
i
g
h
-
q
u
alit
y
w
a
v
ef
o
r
m
g
en
er
atio
n
s
u
itab
le
f
o
r
a
w
id
e
r
an
g
e
o
f
a
p
p
licatio
n
s
t
h
at
r
eq
u
ir
e
s
tab
le
an
d
p
r
ec
is
e
a
n
alo
g
s
ig
n
al
s
.
T
h
e
ch
o
ice
o
f
th
e
DAC0
8
0
8
w
a
s
m
ad
e
d
u
e
to
its
h
ig
h
p
er
f
o
r
m
a
n
ce
,
p
ar
ticu
lar
l
y
i
n
ter
m
s
o
f
r
eso
lu
tio
n
a
n
d
s
i
g
n
al
f
id
elit
y
,
w
h
ic
h
is
es
s
en
tial f
o
r
ap
p
licati
o
n
s
w
h
er
e
w
a
v
e
f
o
r
m
p
r
ec
is
io
n
is
cr
itical
[
1
6
]
.
2.
M
E
T
H
O
D
T
h
e
MI
MA
S
V2
is
a
n
FP
G
A
d
ev
e
lo
p
m
en
t
b
o
ar
d
th
at
in
teg
r
ates
t
h
e
A
MD
Sp
ar
tan
-
6
XC
6
S
L
X9
C
SG3
2
4
,
p
r
o
v
id
in
g
an
e
f
f
ici
en
t
p
lat
f
o
r
m
f
o
r
p
r
o
to
ty
p
i
n
g
an
d
i
m
p
le
m
e
n
ti
n
g
d
ig
ital
d
esig
n
s
.
I
t
f
ea
t
u
r
es
5
1
2
Mb
DDR
SDR
A
M,
allo
w
i
n
g
f
o
r
en
h
a
n
ce
d
d
ata
s
to
r
ag
e
an
d
f
aster
p
r
o
ce
s
s
in
g
ca
p
ab
ilit
ies,
w
h
ich
is
ess
e
n
tial
f
o
r
co
m
p
le
x
ap
p
licatio
n
s
.
A
d
d
itio
n
all
y
,
th
e
b
o
ar
d
in
c
lu
d
e
s
o
n
b
o
ar
d
SP
I
f
lash
u
s
ed
f
o
r
s
to
r
in
g
t
h
e
b
its
tr
ea
m
,
f
ac
ilit
a
tin
g
ea
s
y
co
n
f
ig
u
r
atio
n
a
n
d
r
ep
r
o
g
r
a
m
m
i
n
g
o
f
t
h
e
FP
GA
.
A
d
o
w
n
lo
ad
er
ca
b
le
is
t
y
p
icall
y
e
m
p
lo
y
ed
to
tr
a
n
s
f
er
t
h
e
b
its
tr
ea
m
to
t
h
e
b
o
ar
d
,
en
ab
lin
g
s
tr
aig
h
t
f
o
r
w
ar
d
p
r
o
g
r
a
m
m
in
g
a
n
d
test
i
n
g
.
T
h
i
s
s
etu
p
s
u
p
p
o
r
ts
v
ar
io
u
s
ap
p
lica
tio
n
s
,
i
n
clu
d
i
n
g
DSP
,
e
m
b
ed
d
ed
s
y
s
te
m
s
,
a
n
d
ed
u
ca
tio
n
al
p
r
o
j
ec
ts
,
m
ak
i
n
g
it
a
v
er
s
atile
to
o
l f
o
r
b
o
th
p
r
o
f
ess
i
o
n
als an
d
s
tu
d
e
n
ts
i
n
elec
tr
o
n
i
cs a
n
d
co
m
p
u
ter
e
n
g
i
n
ee
r
i
n
g
[
1
7
]
.
T
h
e
Fig
u
r
e
1
s
h
o
w
t
h
e
u
s
ed
MI
MA
S
V2
FP
GA
d
ev
elo
p
m
en
t
b
o
ar
d
w
h
ich
f
ea
tu
r
e
s
m
u
lt
ip
le
GP
I
O
p
in
s
t
h
at
e
n
ab
le
v
er
s
at
ile
i
n
ter
f
ac
i
n
g
w
it
h
e
x
ter
n
al
d
e
v
ices,
e
n
h
a
n
ci
n
g
its
f
u
n
ctio
n
alit
y
f
o
r
v
ar
io
u
s
ap
p
licatio
n
s
.
A
d
d
itio
n
all
y
,
i
t
in
cl
u
d
es
h
ea
d
er
co
n
n
ec
to
r
s
th
at
s
i
m
p
li
f
y
ac
ce
s
s
to
t
h
ese
p
in
s
,
m
ak
i
n
g
p
r
o
to
ty
p
in
g
an
d
i
n
te
g
r
atio
n
ea
s
ier
f
o
r
d
ev
elo
p
er
s
[
1
7
]
.
T
h
e
Sp
ar
tan
-
6
MI
MA
S
V2
FP
GA
in
teg
r
ate
s
e
m
b
ed
d
ed
in
ter
n
al
s
to
r
ag
e,
u
tili
zin
g
DD
R
SDR
AM
o
p
er
a
tin
g
at
1
6
6
MH
z
w
it
h
a
ca
p
ac
it
y
o
f
5
1
2
Mb
L
P
DDR.
T
h
i
s
t
y
p
e
o
f
m
e
m
o
r
y
i
s
p
ar
ticu
lar
l
y
ad
v
an
ta
g
eo
u
s
f
o
r
ap
p
licatio
n
s
r
eq
u
ir
i
n
g
f
ast
d
ata
ac
ce
s
s
a
n
d
s
to
r
ag
e,
as
i
t
allo
w
s
f
o
r
e
f
f
icie
n
t
h
an
d
li
n
g
o
f
lar
g
er
d
ata
s
et
s
.
E
ac
h
b
lo
ck
i
n
t
h
e
D
DR
SDR
A
M
is
d
esi
g
n
ed
as
s
i
m
p
le
d
u
al
-
p
o
r
t
(
SDP
)
R
AM
,
w
h
ich
e
n
ab
les
s
i
m
u
lta
n
e
o
u
s
r
ea
d
an
d
w
r
ite
o
p
er
atio
n
s
.
T
h
is
ar
ch
itec
tu
r
e
s
ig
n
i
f
ica
n
tl
y
e
n
h
a
n
ce
s
p
er
f
o
r
m
an
ce
b
y
allo
w
i
n
g
t
h
e
FP
GA
to
p
r
o
ce
s
s
m
u
ltip
le
d
ata
s
tr
ea
m
s
co
n
cu
r
r
e
n
tl
y
,
m
ak
in
g
it
id
ea
l
f
o
r
h
ig
h
-
s
p
e
ed
ap
p
licatio
n
s
s
u
c
h
as
DSP
,
r
ea
l
-
ti
m
e
d
ata
ac
q
u
is
itio
n
,
an
d
o
th
er
co
m
p
u
te
-
in
te
n
s
i
v
e
ta
s
k
s
.
T
h
is
FP
G
A
b
o
ar
d
f
ea
tu
r
es
2
K
×
8
-
b
it
p
o
r
t
B
R
A
M
co
n
f
ig
u
r
ed
as
S
D
P
ar
ch
it
ec
tu
r
e.
T
h
is
d
esi
g
n
allo
w
s
f
o
r
s
i
m
u
lta
n
eo
u
s
r
ea
d
an
d
w
r
ite
ac
ce
s
s
,
en
h
an
ci
n
g
d
ata
th
r
o
u
g
h
p
u
t.
T
h
e
B
R
A
M
s
er
v
es
as
a
L
UT
f
o
r
d
ig
ital
s
a
m
p
le
s
s
to
r
ag
e,
e
n
a
b
lin
g
r
ap
id
r
etr
iev
al
o
f
t
h
e
p
r
e
-
d
ef
i
n
ed
v
al
u
es.
T
ab
le
1
s
u
m
m
ar
izin
g
t
h
e
ch
ar
ac
ter
is
tic
s
o
f
s
i
n
g
l
e
p
o
r
t
B
R
A
M
i
n
th
e
Sp
ar
ta
n
-
6
FP
G
A
[
1
8
]
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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&
E
m
b
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d
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Sy
s
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I
SS
N:
2089
-
4864
S
P
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–
field
p
r
o
g
r
a
mma
b
l
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Fig
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Mi
m
as V2
Sp
ar
tan
-
6
FP
GA
d
ev
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H=
0
0
0
0
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0
₂
t
o
3
FH=1
1
1
1
1
1
₂,
a
6
-
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it
co
u
n
ter
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s
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eq
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ate
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ad
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r
ess
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it
h
ea
c
h
i
n
cr
e
m
en
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Fo
r
th
at
w
e
d
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lar
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th
e
v
ar
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le
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a
s
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n
teg
er
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g
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0
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3
to
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ll
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r
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m
a
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le
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3
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teg
er
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th
e
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u
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ter
in
co
r
p
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ates
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as
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s
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E
SET
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tu
r
e,
w
h
ich
en
s
u
r
e
s
th
at
th
e
R
E
SE
T
test
tak
es
p
r
io
r
ity
o
v
er
th
e
c
lo
ck
(
C
L
K)
s
i
g
n
al.
T
h
is
m
ea
n
s
th
a
t
w
h
en
e
v
er
t
h
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R
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ig
n
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ated
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n
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m
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et
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ac
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itial
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eg
ar
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o
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t
h
e
clo
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's
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tat
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s
.
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u
ch
p
r
io
r
it
y
f
o
r
th
e
R
E
SET
s
ig
n
al
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s
cr
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cial
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o
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en
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r
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s
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te
m
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tab
ilit
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a
n
d
p
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g
er
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g
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u
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g
p
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p
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e
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ce
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itio
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s
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m
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n
ti
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co
m
m
o
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p
r
ac
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in
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ig
ital
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esig
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ce
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eli
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ilit
y
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d
co
n
tr
o
l
o
v
er
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n
ter
b
eh
av
io
r
[
2
2
]
.
A
s
th
e
co
u
n
ter
p
r
o
g
r
ess
es,
it
e
f
f
ec
ti
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s
t
h
e
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ed
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ata
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o
m
th
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OM
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D
A
C
0
8
0
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p
u
t.
T
h
e
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at
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d
eliv
er
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p
ee
d
is
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ir
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tly
p
r
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p
o
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tio
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o
th
th
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ter
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e
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OM
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tp
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t
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p
ab
ilit
y
,
to
av
o
id
d
is
to
r
tio
n
at
th
e
DAC
o
u
tp
u
t,
it
'
s
es
s
e
n
tial
to
li
m
i
t
th
e
clo
ck
s
p
ee
d
to
p
r
ev
en
t
ex
ce
ed
in
g
th
e
s
le
w
r
a
te
o
f
th
e
DAC.
T
h
e
s
le
w
r
ate
is
th
e
m
ax
i
m
u
m
r
ate
at
w
h
ic
h
th
e
o
u
tp
u
t
o
f
t
h
e
DAC
ca
n
c
h
an
g
e,
an
d
e
x
ce
ed
in
g
th
is
r
ate
ca
n
lead
to
er
r
o
r
s
in
s
ig
n
al
r
ep
r
o
d
u
ctio
n
.
I
f
th
e
clo
ck
s
p
ee
d
is
to
o
h
ig
h
,
th
e
D
AC
m
a
y
n
o
t
b
e
ab
le
t
o
tr
ac
k
th
e
r
a
p
id
ly
c
h
an
g
i
n
g
i
n
p
u
t
s
i
g
n
als,
r
esu
l
t
in
g
i
n
d
is
to
r
tio
n
o
r
in
ac
cu
r
ate
o
u
tp
u
t
w
a
v
e
f
o
r
m
s
[
2
3
]
,
[
2
4
]
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
n
t J
R
ec
o
n
f
i
g
u
r
ab
le
&
E
m
b
ed
d
ed
Sy
s
t
I
SS
N:
2089
-
4864
S
P
A
R
TAN
–
field
p
r
o
g
r
a
mma
b
l
e
g
a
te
a
r
r
a
y
imp
leme
n
ta
tio
n
fo
r
a
n
a
lo
g
…
(
Mo
u
la
i Kh
a
tir
A
h
med
N
a
s
s
im
)
601
Fig
u
r
e
2
.
Flo
w
c
h
ar
t
o
f
VHD
L
d
escr
ip
tio
n
A
D
R
is
d
ec
lar
ed
in
th
e
e
n
tit
y
o
f
o
u
r
p
r
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g
r
am
as
an
i
n
o
u
t
S
T
D_
L
OGI
C
_
VE
C
T
OR
(
5
d
o
w
n
to
0
)
to
s
er
v
e
as
a
b
id
ir
ec
tio
n
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p
o
r
t
f
o
r
p
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o
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id
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g
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ess
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th
e
R
OM
.
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h
is
co
n
f
ig
u
r
atio
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e
s
s
e
n
tial
f
o
r
ad
d
r
ess
m
an
a
g
e
m
e
n
t
in
m
e
m
o
r
y
ar
c
h
itect
u
r
e,
en
ab
lin
g
b
o
th
r
ea
d
in
g
f
r
o
m
an
d
w
r
i
tin
g
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e
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o
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ca
tio
n
s
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m
p
le
m
e
n
ti
n
g
a
h
i
g
h
-
s
tate
as
y
n
c
h
r
o
n
o
u
s
R
E
SET
is
cr
u
c
ial
f
o
r
en
s
u
r
in
g
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h
at
t
h
e
co
u
n
ter
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ates
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h
e
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itio
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k
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h
et
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er
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eset=1
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f
tr
u
e,
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ar
s
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lip
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n
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r
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r
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k
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f
r
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o
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ac
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ated
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e
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esig
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r
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s
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ch
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o
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a
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is
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n
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e
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n
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s
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g
n
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n
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g
a
r
i
s
in
g
ed
g
e,
t
h
e
d
esig
n
ac
ce
s
s
es t
h
e
co
r
r
esp
o
n
d
in
g
L
UT
v
alu
e
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ca
ted
at
th
e
i
n
d
ex
o
f
t
h
e
cn
t a
r
r
a
y
.
T
h
is
v
alu
e
i
s
t
h
en
co
n
v
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ted
t
o
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u
n
s
i
g
n
ed
8
-
b
it
f
o
r
m
at
a
n
d
ass
ig
n
ed
to
th
e
lu
t_
s
i
g
s
i
g
n
a
l [
2
5
]
.
A
t
t
h
e
en
d
o
f
ea
c
h
p
r
o
ce
s
s
ex
ec
u
t
io
n
o
f
o
u
r
VHD
L
b
eh
av
io
r
al
d
escr
ip
tio
n
,
w
e
m
u
s
t
ass
ig
n
t
h
e
r
esu
lti
n
g
v
al
u
e
o
f
lu
t_
s
ig
,
co
n
v
er
ted
to
ST
D_
L
OGI
C
_
VE
C
T
OR
,
to
th
e
Sin
_
OUT
s
i
g
n
al,
w
h
ic
h
is
d
ec
lar
ed
as
an
o
u
tp
u
t
i
n
o
u
r
e
n
ti
t
y
.
T
h
is
s
tep
is
cr
u
cial
f
o
r
g
e
n
er
ati
n
g
t
h
e
co
r
r
esp
o
n
d
in
g
a
n
alo
g
s
ig
n
al
f
r
o
m
d
i
g
ita
l
r
ep
r
esen
tatio
n
.
T
h
e
f
lo
w
ch
ar
t
in
Fi
g
u
r
e
2
s
u
m
m
ar
izes
t
h
e
d
esig
n
s
tep
s
i
n
v
o
l
v
ed
,
w
h
ile
Fig
u
r
e
3
illu
s
tr
ates
w
a
v
e
f
o
r
m
s
i
m
u
la
tio
n
s
w
it
h
R
OM
ad
d
r
ess
e
s
(
A
D
R
)
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an
g
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g
f
r
o
m
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to
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d
iv
id
e
d
in
to
t
w
o
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i
g
u
r
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s
Fig
u
r
e
3
(
a
)
f
r
o
m
0
0
to
0
B
an
d
Fig
u
r
e
3
(
b
)
f
r
o
m
3
5
to
3
F,
co
n
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u
cted
u
s
in
g
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te
s
t
b
en
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h
i
n
Xilin
x
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SE,
w
h
ic
h
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a
s
i
m
u
latio
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v
ir
o
n
m
e
n
t
u
s
ed
to
v
er
i
f
y
th
e
f
u
n
ctio
n
ali
t
y
o
f
d
ig
ita
l
d
esi
g
n
s
.
I
t
co
n
tai
n
s
th
e
i
n
s
ta
n
tia
tio
n
o
f
th
e
d
esig
n
u
n
d
er
test
(
DUT
)
alo
n
g
w
it
h
s
ti
m
u
l
u
s
s
i
g
n
a
ls
a
n
d
in
p
u
t
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ec
to
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s
to
ex
er
cise
th
e
DUT
.
T
h
e
test
b
en
ch
g
e
n
er
ates
in
p
u
t
an
d
m
o
n
ito
r
s
o
u
tp
u
t
s
,
allo
w
i
n
g
d
esig
n
er
s
to
an
al
y
ze
th
e
b
eh
a
v
io
r
o
f
th
eir
d
esig
n
b
ef
o
r
e
i
m
p
le
m
en
ta
tio
n
o
n
h
ar
d
w
ar
e.
T
h
is
p
r
o
ce
s
s
h
elp
s
id
en
ti
f
y
er
r
o
r
s
an
d
e
n
s
u
r
es
t
h
at
th
e
d
esi
g
n
m
ee
t
s
s
p
ec
i
f
icatio
n
s
.
I
t
d
o
es
n
o
t
r
eq
u
ir
e
p
h
y
s
ical
h
ar
d
w
ar
e
an
d
r
u
n
s
en
tire
l
y
w
it
h
i
n
th
e
s
i
m
u
latio
n
en
v
ir
o
n
m
e
n
t [
2
6
]
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
SS
N
:
2
0
8
9
-
4864
I
n
t J
R
ec
o
n
f
i
g
u
r
ab
le
&
E
m
b
ed
d
ed
Sy
s
t
,
Vo
l.
14
,
No
.
3
,
No
v
e
m
b
er
20
25
:
597
-
604
602
(
a)
(
b
)
Fig
u
r
e
3
.
W
av
ef
o
r
m
s
i
m
u
latio
n
w
it
h
R
OM
ADR
f
r
o
m
(
a)
0
0
to
0
B
an
d
(
b
)
3
5
to
3
F
3.
RE
SU
L
T
S AN
D
D
I
SCU
SS
I
O
N
T
o
v
is
u
alize
o
u
r
ex
p
er
i
m
e
n
tal
r
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lt
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o
f
an
alo
g
w
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e
f
o
r
m
s
o
b
tain
ed
at
th
e
o
u
tp
u
t
o
f
th
e
DAC
s
h
o
w
n
in
F
ig
u
r
e
4
,
w
e
u
s
e
Vi
v
ad
o
d
esig
n
s
u
ite
w
h
ich
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r
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id
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co
m
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en
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v
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et
o
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t
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ls
f
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h
ar
d
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ar
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d
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ip
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n
,
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y
n
t
h
esi
s
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s
i
m
u
lat
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n
,
an
d
p
r
o
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r
a
m
m
i
n
g
o
f
Xili
n
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e
v
ices.
Vi
v
ad
o
is
a
n
ad
v
a
n
ce
d
I
DE
b
y
Xili
n
x
,
d
esig
n
ed
f
o
r
cr
ea
tin
g
co
m
p
le
x
FP
GA
d
esig
n
s
,
esp
ec
iall
y
f
o
r
n
e
w
er
f
a
m
ilie
s
lik
e
th
e
7
-
s
er
ies,
Ultr
aSca
le,
an
d
Ver
s
al.
T
h
ese
FP
G
A
f
a
m
i
lies
o
f
f
er
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i
g
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p
er
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an
ce
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p
o
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n
s
u
m
p
t
io
n
,
w
it
h
Viv
ad
o
o
p
ti
m
izi
n
g
th
eir
ca
p
ab
ilit
ies.
I
t
s
u
p
p
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r
ts
HDL
s
lik
e
VH
D
L
an
d
Ver
ilo
g
,
as
w
ell
as
h
i
g
h
-
lev
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s
y
n
t
h
esis
(
H
L
S)
f
o
r
C
,
C
++
,
an
d
Op
en
C
L
.
Viv
ad
o
en
ab
les
s
y
n
t
h
es
is
,
s
i
m
u
latio
n
,
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d
o
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tim
iza
tio
n
f
o
r
h
i
g
h
-
s
p
e
ed
ap
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licatio
n
s
an
d
in
cl
u
d
es
to
o
ls
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o
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d
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u
g
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n
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l
-
ti
m
e
s
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m
u
lat
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2
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As
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2
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Mi
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RE
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NC
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[
1
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X
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p
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[
2
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[
4
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Y
.
D
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,
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.
L
i
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Y
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L
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