Inter national J our nal of P o wer Electr onics and Dri v e System (IJPEDS) V ol. 17, No. 2, June 2026, pp. 991 ∼ 1007 ISSN: 2088-8694, DOI: 10.11591/ijpeds.v17.i2.pp991-1007 ❒ 991 Optimal selection of curr ent contr ol technique in multiphase DC-DC con v erters f or dynamic load v ariations H. Swathi Hatwar 1,2 , K. Suryanarayana 1,2 , Anup Shetty 1 1 Department of Electrical and Electronics Engineering, NMAM Institute of T echnology (NMAMIT), Nitte (Deemed to be Uni v ersity), Nitte, India 2 V isv esv araya T echnological Uni v ersity , Belag a vi, India Article Inf o Article history: Recei v ed Oct 2, 2025 Re vised Mar 5, 2026 Accepted Apr 23, 2026 K eyw ords: Current balance Current sampling DC-DC con v erter Dual control loop Interlea v ed con v erter MCU based control W ide bandg ap de vice ABSTRA CT Multiphase DC-DC con v erters are widely adopted in high-po wer applications such as electric v ehicles (EVs) and rene w able ener gy systems due to their ability to reduce current ripple, impro v e ef cienc y , and distrib ute thermal stress across multiple phases. Ho we v er , under dynamic load v ariations, mismatches in passi v e components, de vice parameters, parasitic elements, and thermal ef f ects can result in phase current imbalance. This imbalance de grades transient performance, increases circulating currents, and reduces o v erall system reliability . Therefore, selecting an appropriate current control str ate gy is essential to ensure accurate current sharing and stable output v oltage re gulation under v arying operating conditions. This paper presents a comparati v e study and selection methodol ogy for current control techniques for MCU-based interlea v ed DC- DC con v erters. V arious current control strate gies are e v aluated in terms of dynamic response, steady-state current sharing accurac y , implementation comple xity , and embedded feasibility . A 1 kW , 36 V -12 V three-phase interlea v ed b uck con v erter using Gallium Nitride de vices i s modeled in MA TLAB/Simulink and v alidated through hardw are e xpe rimentation. The comparati v e results highlight the trade-of f s among transi ent performance, curr ent balancing accurac y , scalability , and embedded im plementation comple xity , pro viding a structured basis for selecting an appropriate current control technique as per application requirements. This is an open access article under the CC BY -SA license . Corresponding A uthor: K. Suryanarayana Department of Electrical and Electronics Engineering, NMAM Institute of T echnology (NMAMIT) Nitte (Deemed to be Uni v ersity) Nitte - 574110, India Email: suryanarayana@nitte.edu.in 1. INTR ODUCTION The rapid electrication of transportation, dri v en by stringent emission re gulations and t he global transition to w ard sustainable ener gy , has signicant ly increased the demand for high-ef cienc y and high-po wer -density con v ersion systems. In electric v ehicles and h ybrid ener gy platforms, DC-DC con v erters play a critical role in stepping do wn high-v oltage battery le v els to re gulated lo w-v oltage b uses, supplying auxiliary loads, and managing bidirectional ener gy o w between storage elements and po wer electronic subsystems. As these applications require impro v ed ef cienc y , high po wer density , and f ast transient response under dynamic load conditions, interlea v ed multiphase DC-DC con v erters ha v e emer ged as a preferred solution [ 1 ]. By distrib uting the load current across multiple phases with phas e-shifted operation, these con v erters J ournal homepage: http://ijpeds.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
992 ❒ ISSN: 2088-8694 achie v e reduced input and output current ripple, lo wer ltering requirements, impro v ed thermal distrib ution, enhanced dynamic performance, and reliable po wer deli v ery under v arying operating conditions [2]–[4]. Such con v erters typically emplo y a hierarchical control architecture consisting of an outer v oltage loop for output re gulation and an inner current loop for inductor current control and phase current sharing. Current control in DC-DC con v erters is commonly realized using techniques such as peak current mode control (PCMC) and a v erage current mode control (A CMC). PCMC is widely adopted in single-phase b uck and boost con v erters, where it enables direct inductor current re gulation and c ycle- b y- c ycle current monitoring [ 5 ]. A CMC is frequently implemented in multiphase con v erters, po wer f actor correction (PFC) systems, and battery char ging applications, where a v erage inductor current re gulation supports controlled po wer deli v ery and coordinated phase operation [ 6 ], [ 7 ]. W ithin A CMC-based multi phase systems, v arious strate gies such as unied control, indi vidual phase control, and sensorless current control techniques ha v e been proposed to re gulate and distrib ute phase currents ef fecti v ely [ 8 ]–[ 11 ]. These approaches pro vide structured frame w orks for implementing current sharing and re gulation in digitally controlled multiphase con v erters. W ith the adoption of wide-bandg ap (WBG) de vices, control design considerations are chal lenging to accommodate their high-speed switching capabilities. The material properties of WBG de vices enable operation in the MHz switching frequenc y range, of fering high ef cienc y , f ast transient response, reduced passi v e component size, and i ncreased po wer density [ 12 ]–[ 14 ]. These characteristics necessitate appropriately designed current re gulation strate gies capable of operating at ele v ated switchi ng frequencies with precise timing coordination. Digital control of WBG-based con v erters can be implemented using platforms such as eld programmable g ate arrays (FPGAs), microcontrollers (MCUs), and digital signal processors (DSPs). FPGA-based solutions f acilitate high-speed control e x ecution and e xible digital architecture design [ 15 ], [ 16 ]. MCU and DSP-based implementations pro vide inte grated peripheral s, programmable control loops, and streamlined system inte gration, making them widely adopted in industrial po wer electronic applications. Careful design of digital current control algorithms, sampling strate gies, interrupt management, and peripheral conguration plays a k e y role in achie ving ef fecti v e implementation in WBG-based multiphase con v erters. In practical implementations, mismatches in passi v e components, parasitic resistances, de vice characteristics, g ate dri v er timing, and PCB layout asymmetry can lead to non-uniform phase currents. Sampling delays, digital control discretiza tion, and dynamic load v ariations can furt her e xacerbate this imbalance. Persistent current mismatch results in localized thermal hotspots, une v en switching and conduction stress, accelerated de vice ageing, reduced ef cienc y , and compromised long-term reliability of the con v erter system. T o mitig ate the current imbalance, se v eral A CMC-based strate gies ha v e been proposed in the literature, demonstrated through analytical studies, simulations, or FPGA-based digital implementations, where e xible control architecture and parallel processing capabilities can be realized. In contrast, industrial multiphase DC-DC con v erters are predominantly implemented using MCUs and DSPs, o wing to their inte grated peripherals, compact architecture, streamlined rm w are de v elopment, and suitability for cost-ef f ecti v e deplo yment. Ho we v er , a systematic e xperimental e v aluation of dif f erent A CMC-based current balancing strate gies implemented on a resource-constrained MCU platform under identical operating conditions has not been comprehensi v ely reported. This study aims to demonstrate the adv antages and potential dra wbacks of each approach in practical applications, pro viding insights into their implementation and impact on the con v erter performance. T o systematically address the current imbalance in practical implementations, this paper in v es tig ates unied, indi vidual, and decoupled current imbalance control techniques in a three-phase interlea v ed b uck con v erter using an MCU-based digital signal controller . The study focuses on mitig ating the current imbalance under both steady-state and dynamic load conditions. Comprehensi v e simulation and e xperimental v alidation are conducted on a 1 kW , 36 V -12 V GaN-based prototype to e v aluate current sharing performance and real-time digital implementation aspects of each control strate gy . 2. METHOD This section presents the detailed mathematical modeling of the three-phase interlea v ed DC-DC con v erter . A state-space approach is emplo yed to deri v e the small-signal transfer function. Current control strate gies for impro ving dynamic and steady-state performance are analyzed. The o v erall system design and control implementation are described. F or real-time realization, the MCU-based current sampling and control algorithm e x ecution o w is presented. Int J Po w Elec & Dri Syst, V ol. 17, No. 2, June 2026: 991–1007 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 993 2.1. Mathematical modelling of interlea v ed con v erter In an interlea v ed b uck topology , multiple b uck con v erters operate in parallel with a phase shift between the switching signals, thereby distrib uting the load current among the phases. The circuit diagram of the three-phase interlea v ed synchronous b uck con v erter considering parasitic elements i s sho wn in Figure 1(a). In the interlea v ed topology , the phase angle between each phase w as determined by the number of phases. Using the relationship 360 ◦ /N (where N is the number of phases) for a three-phase interlea v ed topology , the phase angle dif ference between each phase is 120 ◦ . F or con v erter analysis, uniform loss components and equal per -phase inductances are considered as gi v en in (1) - (3) . F or the switching period T s , the con v erter operates in six distinct modes, as depicted in Figure 1(b) with tw o top-switches and an opposite phase bottom switch ON in 3 modes and an y one top switch and the other tw o phases bottom switches ON in the remaining 3 modes of operation. L 1 = L 2 = L 3 = L (1) R L 1 = R L 2 = R L 3 = R L (2) R ds 1 T = R ds 2 T = R ds 3 T = R ds 1 B = R ds 2 B = R ds 3 B = R ds (3) The state equations for inductor and capacitor and output equation in mode 1, 3 and 5 (an y tw o top switches are ON) could be written as in (4)-(6). L di L ( t ) dt = 2 V g ( t ) − R ds + R L + 3 R R c R + R c i L ( t ) − 3 R R + R c v c ( t ) (4) C dv c ( t ) dt = R R + R c i L ( t ) − 1 R + R c v c ( t ) (5) v ( t ) = R R c R + R c i L ( t ) + R R + R c v c ( t ) (6) The state equations for inductor and capacitor , and output equations in mode 2, 4 and 6 (only one of the top switch is ON) could be written as in (7)-(9). L di L ( t ) dt = V g ( t ) − R ds + R L + 3 R R c R + R c i L ( t ) − 3 R R + R c v c ( t ) (7) C dv c ( t ) dt = R ( R + R c ) i L ( t ) − 1 R + R c v c ( t ) (8) v ( t ) = R R c R + R c i L ( t ) + R R + R c v c ( t ) (9) (a) (b) Figure 1. Three-phase interlea v ed b uck con v erter: (a) mathematical model and (b) timing diagram Optimal selection of curr ent contr ol tec hnique in multiphase DC-DC con verter s for ... (H. Swathi Hatwar) Evaluation Warning : The document was created with Spire.PDF for Python.
994 ❒ ISSN: 2088-8694 From the timing diagram, the con v erter operates in modes 1, 3, and 5 for a duration of ( 2 3 − d ′ ) , and in modes 2, 4, and 6 for a duration of ( d ′ − 1 3 ) , where d ′ = 1 − d . Using the state-space a v eraging technique, the steady-state equations can be obtained as in (10)-(13) [17]. A = A 1 (2 − 3 d ′ ) + A 2 (3 d ′ − 1) (10) B = B 1 (2 − 3 d ′ ) + B 2 (3 d ′ − 1) (11) C = C 1 (2 − 3 d ′ ) + C 2 (3 d ′ − 1) (12) E = E 1 (2 − 3 d ′ ) + E 2 (3 d ′ − 1) (13) The state space and output equation in the ON state is gi v en as in (14) and (15). L 0 0 C di L ( t ) dt dv c ( t ) dt = − R ds + R L + 3 R R c R + R c − 3 R R + R c R R + R c − 1 R + R c i L ( t ) v c ( t ) + 2 0 v g ( t ) (14) v ( t ) i L ( t ) = R R c R + R c R R + R c 1 0 i L ( t ) v c ( t ) + 0 0 v g ( t ) (15) State space and output equation in the OFF state is gi v en as in (16) and (17). L 0 0 C di L ( t ) dt dv c ( t ) dt = − R ds + R L + 3 R R c R + R c − 3 R R + R c R R + R c − 1 R + R c i L ( t ) v c ( t ) + 1 0 v g ( t ) (16) v ( t ) i L ( t ) = R R c R + R c R R + R c 1 0 i L ( t ) v c ( t ) + 0 0 v g ( t ) (17) Applying Laplace transform, open loop transfer functions could be deri v ed using (18)-(21). ˆ y ( s ) = C sI − K − 1 A − 1 K − 1 F + G ˆ d ( s ) (18) F = ( A 1 − A 2 ) X + ( B 1 − B 2 ) U (19) G = ( C 1 − C 2 ) X + ( E 1 − E 2 ) U (20) X = − A − 1 B U (21) The transfer functions, output v oltage to control G v d ( s ) and inductor current to control G id ( s ) of the three-phase interlea v ed synchronous b uc k con v erter , considering dominant loss components, are deri v ed and gi v en by (22) and (23) [17]. G v d ( s ) = ˆ v ( s ) ˆ d ( s ) = R R c C V g s + R V g D en (22) G id ( s ) = b i L ( s ) ˆ d ( s ) = ( R C V g + R c C V g ) s + V g D en (23) Where, D en = ( R LC + R c LC ) s 2 + ( L + 3 R R c C + R R L C + R c R ds C + R c R L C + R R ds C ) s + (3 R + R L + R ds ) The transfer function between inductor current and output v olt age G v i ( s ) can be deri v ed using (22) and (23) and gi v en as in (24). G v i ( s ) = ˆ v ( s ) b i L ( s ) = R R c C V g s + R V g ( R C V g + R c C V g ) s + V g (24) Int J Po w Elec & Dri Syst, V ol. 17, No. 2, June 2026: 991–1007 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 995 2.2. Curr ent contr ol techniques Ef fecti v e current control techniques in m ultiphase con v erters play a vital role in enhancing ef cienc y , reliability , and o v erall system performance. Adv anced control strate gies minimize current ripple and EMI, ensuring signal inte grity in high-speed applications. Furtherm ore, accurate current control f acilitates optimal con v erter operation under v arying load conditions, supports compact component sizing, simplies thermal design, and enables scalable and cost-ef f ecti v e system architectures. The follo wing section e xplores the widely adopted current control methods and their impact on the multiphase con v erter performance, highlighti ng MCU implementation aspects.the 2.2.1. Unied curr ent contr ollers In the unied current control technique, a single current controller go v erns all con v erter phases by generating a common duty c ycle d . The system typically emplo ys a cascaded structure, consisting of an outer v oltage re gulation loop P I v and an inner c urrent compensator loop P I i as sho wn in Figure 2(a). This approach requires only a single current sensor independent of the number of phases. Ho we v er , as a common duty c ycle is applied to each of the phases, this method cannot acti v ely compensate for current mismat ches arising from de vice parameter v ariations, parasitic elements, or dynamic load transients that may lead to unequal current sharing among phases. Furthermore, in the unied control structure, a f ault in an y indi vidual phase af f ects the entire system, potentially de grading o v erall system performance. 2.2.2. Indi vidual curr ent contr ollers Indi vidual current control technique incorporates a dedicated current controller to each phase P I 1 , P I 2 ,... P I N as sho wn in Figure 2(b). The outer controller P I v re gulates the o v erall output v oltage and generates a total current reference ( I r ef ), which is distrib uted across N phases. Each phase controller then re gulates the respecti v e inductor current independently . This ensures precise current shari ng, enhances f ault tolerance as the f aulty phase can be isolated, and impro v es rob ustness under dynamic load or component parameter v ariation. Ho we v er , it a dds comple xity due to the need for multipl e current sensors, synchronized current sampling, and an increased number of current controllers, leading to higher computational comple xity as the number of phases increases. Despite being computationally e xpensi v e and comple x, this method is superior in applications demanding tight current balancing and resilience to phase f aults. 2.2.3. Unied curr ent contr oller with PI-based imbalance compensators In this method, inductor current of each phase ( i L 1 , i L 2 ... i LN ) is continuously monitored, and a proportional-inte gral controller ( P I comp ) computes the correction duty c ycle of each phase in real-time based on the de viation from the a v erage phase current ( i av g ) . This correction loop operates at the same rate as the current controller , allo wing it to quickly balance phase currents during transients or dynamic load v ariations. The duty c ycle correction f actor of each phase is computed through a dedicated correction loop thus ensuring balanced current across the loop. While it ensures e xcellent transient and steady-state current shar ing, additional PI control tuning and e x ecution add to the control comple xity . The system model is as in Figure 3(a). (a) (b) Figure 2. System model with (a) unied current controller and (b) indi vidual current controller 2.2.4. Unied curr ent contr oller with corr ection factor -based imbalance compensators This method utilizes a correction f actor (K) to adj ust each phase’ s duty c ycle based on imbalance, enabling steady-state accurac y with lo wer computational demand [ 18 ]. This control technique can be Optimal selection of curr ent contr ol tec hnique in multiphase DC-DC con verter s for ... (H. Swathi Hatwar) Evaluation Warning : The document was created with Spire.PDF for Python.
996 ❒ ISSN: 2088-8694 implemented as in Figure 3(b). The per -phase inductor currents are measured and fed to the corresponding correction f actor loop that compares the a v erage current i av g = I r ef N , where N i s the total number of phases. Then the de viation from reference current is computed using (25). ∆ I N = I N − I av g (25) The duty c ycle correction f actor is computed using (26). ∆ D N = ∆ D N + K ∗ ∆ I N (26) The correction f actor K can be selected based on the speed of compensation required. The per -phase duty c ycle is computed using (27). D N = D base − ∆ D N (27) Since duty c ycle adjustment must be applied to each phas e indi vidually , this method may add computational o v erhead to the MCU and may af f ect real-time performance. T o mitig ate this, duty correction is e x ecuted at a slo wer rate than the main current and v oltage control loop e x ecution rate. Thus, this method incorporates the adv a ntages of a unied current controller at a lo wer CPU resource requirement and the steady state current balancing capability of the indi vidual current controller . This technique might introduce a slight response lag during rapid load transients, and it retains the f ault-tolerant benets of indi vidual current controllers. Moreo v er , only the total current sensor requires high bandwidth, while phase current sensors can operate at lo wer bandwidths, reducing o v erall system cost. (a) (b) Figure 3. System model with (a) PI-based current imbalance compensator and (b) correction-f actor -based current compensator 2.3. System description The system emplo ys a three-phase interlea v ed b uck con v erter with GaN switches (S1T , S2T , S3T , S1B, S2B, and S3B). The control signals for the switches are generat ed using an NXP MC56F84789 DSC. The DSC houses tw o multichannel f ast 12-bit ADCs that enable accurate current and v oltage measurement. Its inte grated peripherals and ample computational resources f acilitate ef cient real-time control in a compact and cost-ef fecti v e implementation [19]. A block diagram of the proposed system is as in Figure 4. The design specications of the con v erter for the desired ratings are gi v en in T able 1. The inductor and capacitor v alues are cal culated a ccording to standard design procedure [ 20 ], [ 21 ]. T o support high-frequenc y operation with minimal core losses, inductors are w ound on MP3310MPFC Metgl as amorphous allo y cores, selected for their lo w loss characteristics up to 500 kHz, high saturation ux densi ty , and thermal stability . Current sensing is performed using Hall-ef fect sensors, pro viding g alv anic isolation, high bandwidth, and inte grated f ault outputs. V oltage feedback is obtained via resistor di viders, conditioned through dif f erential ampliers to ensure accurac y and noise immunity before ADC con v ersion, enabling precise control and prot ection of the con v erter . Int J Po w Elec & Dri Syst, V ol. 17, No. 2, June 2026: 991–1007 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 997 Figure 4. Block diagram of three-phase interlea v ed b uck con v erter with digital controller T able 1. Con v erter specications Symbol Description Desired v alue P o Output po wer 1 kW V g Input v oltage 36 V η Ef cienc y 95% (assumed) v Output v oltage 12 V f s Nominal switching frequenc y 100 kHz δ Current ripple per phase 25% of a v erage current B max Maximum ux density of Metglas core 1.5 T L ph Inductance per phase 11 µ H C Output capacitance 10 µ F δ V Peak to peak ripple in output v oltage 1 % R L Measured DC resistance of inductor 10 m Ω R c ESR of capacitor 6 m Ω 2.4. Contr oller design The cascade control scheme is being adopted in this research w ork, with current bei ng the inner loop and v oltage as the outer loop. The standard cascade control design guidelines recommend setting the inner current loop bandwidth ( B W cc ) up to one-tenth of the switching frequenc y ( f sw ) and the outer v oltage loop bandwidth ( B W v c ) up to one-fth of the current loop bandwidth. This hierarchical structure ensures an ef fecti v e decoupling between the tw o c o nt rol loops so that each could be indi vidually tuned, allo wing the inner loop to respond signicantly f aster than the outer loop. The controller parameters are selected such that the bandwidth of the inner current loop is approximately 2.42 kHz. Thus, the coef cients of the inner current re gulating controller are selected as Kp = 0.001 and Ki = 200 to attain the desired phase mar gin of 75 ◦ . The outer v oltage l oop control parameters are selected as Kp = 0.5 and Ki = 20000 with a bandwidth of 460 Hz with a phase mar gin of 90 ◦ . The bode plot of current loop G id and v oltage loop G v i is generated using MA TLAB as in Figures 5(a) and 5(b). F or digital implem entation, the discrete-time transfer functions of the compensated system with a sampling period of 10 µ s. 2.5. Digital implementation The practical d e plo yment of the proposed control strate gies necessitates a rob ust digital implementation frame w ork to translate theor etical control la ws into real-time hardw are operation. Digital implementation plays a crucial role in ensuring accurate current re gulation, synchronized phase operation, and reliable performance under dynamic load conditions. Ho we v er , achie ving this in a multiphase con v erter introduces challenges such Optimal selection of curr ent contr ol tec hnique in multiphase DC-DC con verter s for ... (H. Swathi Hatwar) Evaluation Warning : The document was created with Spire.PDF for Python.
998 ❒ ISSN: 2088-8694 as precise timing coordination, sampling synchronization, computational latenc y , and peripheral resolution constraints. This section presents the digital implementation architecture, outlining the adopted current sampling methodology , PWM generation scheme, and resolution considerations, interrupt scheduling, and softw are-le v el synchronization mechanisms required for stable and deterministic real-time control. -100 -50 0 50 Magnitude (dB) 10 2 10 3 10 4 10 5 10 6 10 7 -135 -90 -45 0 Phase (deg) Gid I_inner Bode Diagram Frequency  (Hz) 75 deg @  2.42 kHz (a) -60 -40 -20 0 20 Magnitude (dB) 10 2 10 3 10 4 10 5 10 6 10 7 -135 -90 -45 0 Phase (deg) Gvi V_outer Bode Diagram Frequency  (Hz) 93.9 deg @ 460 Hz (b) Figure 5. Bode plot of (a) current loop and (b) v oltage loop 2.5.1. Curr ent sampling techniques Accurate current sampling is essential for precise current control and f ault detection in digitally controlled po wer con v erters, as measurement errors can af fect duty c ycle adjustments and improper load sharing in multiphase con v erters. One of the techniques is to sample the inductor current at the center of the PWM on-time, as sho wn in Figure 6(a). This requires separate ADC trigger pulses for each phase to capture a v erage currents. Sensor latenc y introduces a delay between actual and measured currents, which can be compensated for by adjusting the sampling instant. This method requires PWM–synchronized triggering, and as the phase count increases, ADC sampling rate limitations may restrict its applicability . The second method emplo ys RC lo w-pass lters to e xtract the DC a v erage inductor current, as sho wn in Figure 6(b). This technique lifts the board requirement of sampling instances in a switching c ycle. Its k e y adv a ntage is the ability to simultaneously sample all N-phase currents, making it suitable for compl e x multiphase systems. The ADC implementation in this paper utilizes the hardw are lter scheme. Actual Current Measured Current t offset i L 1 , i L 2 , i L 3 time T s time i L 1 ( avg ) , i L 2 ( avg ) , i L 3 ( avg ) (a) (b) i L 1 , i L 2 , i L 3 Figure 6. Current sampling techniques: (a) at center of PWM and (b) with hardw are a v eraging Int J Po w Elec & Dri Syst, V ol. 17, No. 2, June 2026: 991–1007 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 999 2.5.2. Softwar e implementation In digital control implementations, PWM resolution directly inuences the granularity with which the duty c ycle can be adjuste d in real time. It is determined by the ratio of the timer clock frequenc y f cl k to the switching frequenc y f sw , which denes the number of discrete timer counts a v ailable within one PWM period. F or a controller with a x ed f cl k , the a v ailable timer counts per PWM period N decrease as f sw increases, reducing the resolution. This in v erse relationship limits duty c ycle precision at higher switching frequencies, which is particularly critical for GaN-based con v erters requiring ner control. In the present implementation, the selected MCU operates with a clock frequenc y of 100 MHz and a switching frequenc y of 100 kHz, resulting in 1000 timer c o unt s per PWM period. This denes the ef fecti v e PWM resolution a v ailable for digital duty-c ycle modulation in the proposed system. In real-time control systems, precise synchronization between PWM signals, ADC sampling, a nd control loop e x ecution is critical for accurate and ef cient operation. The de v eloped system emplo ys a PWM timer counter with predened comparison v alues to trigger synchronized e v ents across all the three PWM generation modules. ADC con v ersions are initiated by PWM trigger signals at specic instances, follo wed by interrupt service routines (ISR) that process sampled data, compute control parameters, and update duty c ycles. F or the de v eloped three –ph a se interlea v ed con v erter , three PWM submodules (SM0, SM1, SM2) of the PWMA module are used for PWM generation, with SM0 as the master submodule while SM1 and SM2 are phase-shifted by 120 ◦ and 240 ◦ , respecti v ely , with respect to SM0 ensuring proper synchronization for interlea v ed operation. The V AL1 re gister in SM0 determines the PWM switching frequenc y f sw , whereas V AL2 and V AL3 dene the rising and f alling edges respecti v ely to control the duty c ycle d(t). The V AL4 and V AL5 re gisters in SM0 were used to generate synchronization triggers (PWMA0 TRIG0 and PWMA0 TRIG1) for phase-shifting SM1 and SM2, ensuring an interlea v ed operation as indicated in Figure 7. SM1 TRIG0 w as used to trigger the ADC con v ersion at the center of the PWM c ycle, ensuring accurate current sampling. W ithin the ADC ISR, pa rameters such as v oltages and currents are measured, and the duty c ycle is computed. After the computation, the updated duty c ycle v a lues are pre-loaded to the PWM v alue re gisters, which wil l be loaded during the ne xt c ycle. T o ensure synchronized updates, the LDOK (Load OK) bits are set, allo wing the updated duty c ycle v al ues to be loaded at the start of the ne xt PWM c ycle. The softw are is de v eloped in NXP IDE (CodeW arrior) using embedded ’C’ coding. V AL1 V AL5 V AL3 V AL4 INIT Ext. sync for SM1  TRIG0 SM0 Ext. sync for SM2  TRIG1 SM0 SM0 SM1 V AL2 V AL3 V AL2 V AL3 SM2 V AL2 V AL3 SM1  TRIG0 Control loop  computation time ADC Conversion time Figure 7. T iming diagram of digital control implementation 3. RESUL TS AND DISCUSSION This section e v aluat es the ef f ecti v eness of the proposed current balanci ng technique under steady-state and dynamic operating conditions, which is v alidated through detailed simulations and hardw are e xperimentation. The con v erter performance is a n a lyzed in terms of phase current distrib ution, duty c ycle adaptation, and transient reco v ery during load v ariations. Optimal selection of curr ent contr ol tec hnique in multiphase DC-DC con verter s for ... (H. Swathi Hatwar) Evaluation Warning : The document was created with Spire.PDF for Python.
1000 ❒ ISSN: 2088-8694 3.1. Simulation r esults The interlea v ed synchronous b uck con v erter of T able 1 is simulated using MA TLAB Simulink to e v aluate the inherent current sharing capability and rob ustness of dif ferent current control strate gies as in Figure 8. In simulation, a ± 10% v ariation in the inductor resistance is introduced that w ould closely resemble hardw are beha vior . W ith unied current control, a signicant current imbalance is observ ed across phases, with a v erage phase currents of 19.31 A ( p ha se 1), 17.99 A (phase 2), and 16.74 A (phase 3) ag ainst the e xpected 18.01 A, and a ripple curr ent of 7.24 A as in Figure 9(a). This will lead to a higher temperature in the neighborhood of phase 1 traces compared to phase 3. Also, the stress on the phase 1 switches will be comparati v ely higher and the situation will w orsen as the load current increases. In contrast, t he indi vidual current control technique achie v ed uniform current shari ng, with an a v erage of 18.01 A per phase and a ripple current of 7.25 A as in Figure 9(b). Current balance w as maintained e v en under transient conditions, demonstrating rob ustness and dyn a mic response. Ho we v er , the implementation of this technique in the digital domain demands huge computational resources. The decoupled current imba lance compensator e xhibits transient beha vior similar to unied control, b ut the imbalance loop corrected de viations within 2 ms, achie ving balanced steady-sta te currents comparable to indi vidual control as in Figure 9(c). This approach ensures current balance, a v oiding thermal hotspots as the thermal time constant will be higher . Due to e v en temperature distrib ution, it is possible to achie v e better system performance. This conrms its ef fecti v eness in combining computational ef cienc y with accurate current balancing. Figure 8. Simulink model of three-phase interlea v ed b uck con v erter 3.2. Experimental r esults The performance of v arious control techniques is v alidated on a in-house de v eloped t hree-phase interlea v ed c on v erter prototype featuring GaN GS61008P transistors dri v en by LM5113 half-bridge g ate dri v ers [ 22 ], [ 23 ], A CS720 Hall-ef f ect current sensors, v oltage measurement circuitry , on a six-layer PCB measuring 19 cm x 39 cm. The e xperimental setup, including load, current/v oltage probes, and digital storage oscilloscope (DSO), is sho wn in Figure 10. Dynamic response w as tested with resisti v e loads, Figure 10(a), while real-time performance w as v alidated using a 220 AH Li-polymer battery , Figure 10(b). Softw are de v elopment w as carried out in CodeW arrior V10.4 IDE using embedded C programming, with the component ins pector simplifying initialization of modules lik e PWM, ADC, timers, and interrupts. Controller is programmed via JT A G, enabling Int J Po w Elec & Dri Syst, V ol. 17, No. 2, June 2026: 991–1007 Evaluation Warning : The document was created with Spire.PDF for Python.